AUXSRC=clk_sys
Clock control, can be changed on-the-fly (except for auxsrc)
| AUXSRC | Selects the auxiliary clock source, will glitch when switching 0 (clk_sys): undefined 1 (clksrc_pll_sys): undefined 2 (clksrc_pll_usb): undefined 3 (clksrc_gpin0): undefined 4 (clksrc_gpin1): undefined |
| KILL | Asynchronously kills the clock generator, enable must be set low before deasserting kill |
| ENABLE | Starts and stops the clock generator cleanly |
| PHASE | This delays the enable signal by up to 3 cycles of the input clock This must be set before the clock is enabled to have any effect |
| NUDGE | An edge on this signal shifts the phase of the output by 1 cycle of the input clock This can be done at any time |
| ENABLED | clock generator is enabled |